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| dev:zynq7000pl [2021/12/30 08:22] – ursgraf | dev:zynq7000pl [2022/08/22 11:33] (current) – ursgraf | ||
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| ====== PL Configuration on the Zynq7000 ====== | ====== PL Configuration on the Zynq7000 ====== | ||
| - | * Create | + | * Use Xilinx Vivado to create |
| + | * Using Vivado, create a new Zynq7000 project following the instructions in {{ : | ||
| + | * Launch the SDK to create a simple Application, | ||
| + | * Launch the SDK to create a FSBL (first stage boot loader), see {{ : | ||
| + | * Start the //Create Boot Image Tool// and create new BIF file or import existing file. You have to create two different boot files | ||
| + | |||
| + | ==== FSBL / PL ==== | ||
| + | This boot files can be used for [[https:// | ||
| + | * Add // | ||
| + | * Add PL configuration, | ||
| + | * Output format //MCS// | ||
| + | * Create image, e.g. // | ||
| + | * Copy this file to ([[https:// | ||
| + | This image file can be loaded into the QSPI flash, see [[https:// | ||
| + | |||
| + | ==== FSBL / PL / Application ==== | ||
| + | This boot files can be used for [[https:// | ||
| + | * Add // | ||
| + | * Add PL configuration, | ||
| + | * Add hello world // | ||
| + | * Output format //MCS// | ||
| + | * Create image, e.g. // | ||
| + | * Repeat with output format //BIN// | ||
| + | * Create image, e.g. // | ||
| + | * Copy both files to ([[https:// | ||
| + | // | ||